1. Field
Exemplary embodiments of the present invention relate to a technology of manufacturing a semiconductor device, and more particularly, to a semiconductor device capable of preventing off-leakage of a transistor and a semiconductor memory device using the same.
2. Description of the Related Art
A semiconductor device, for example, a semiconductor memory device such as a DRAM, transfers data of memory cells (MC) to bit lines BLs by supplying a specific voltage to word lines WLs for a predetermined time in an active operation mode to activate the word lines WLs and includes a bit line sense amplifier (BLSA) sensing and amplifying data of bit lines. In a read operation mode, the data amplified by the bit line sense amplifier are output to the outside through a data transmission line. Further, in a write operation mode, external data transmitted through the data transmission line are transferred to the bit lines and stored in the memory cells.
Meanwhile, in a precharge operation mode, the device isolates memory cells from the bit lines by supplying the specific voltage to the word lines for a predetermined time to inactivate the word lines and waits until a next active operation mode by precharging the bit lines with precharge voltage (VBLP). For reference, a read operation and a write operation are performed between the active operation and the precharge operation.
Conventional semiconductor memory devices often suffer from deterioration of its characteristics due to off-leakage in the precharge operation mode, which will be described in detail with reference to FIGS. 1, 2A, and 2B.
FIG. 1 is a block diagram schematically illustrating a semiconductor device in accordance with the prior art and FIGS. 2A and 2B are diagrams for describing problems in accordance with the prior art.
As illustrated in FIG. 1, the semiconductor memory device in accordance with the prior art may include a memory unit 110. The memory unit 110 has a plurality of memory cells, each of which comprises a cell transistor 101 and a data storage unit 102 such as a capacitor, a plurality of word lines WLs and a plurality of bit lines BLs connected with the plurality of memory cells. The device may have a word line driver 120 and a bit line sense amplifier 130 each connected with the word lines WLs and the bit lines BLs extending from the memory unit 110.
In accordance with the prior art, in order to suppress the off-leakage of the cell transistor 101 in the precharge operation mode, as illustrated in FIG. 2A, the device increases threshold voltage of the cell transistor 101 by supplying negative voltage, for example, back bias voltage (VBB) lower than ground voltage to a substrate on which the cell transistor 101 is formed while supplying the ground voltage VSS to the word lines WLs, to suppress off-leakage.
However, the back bias voltage VBB supplied to the substrate cannot function as a main factor controlling the threshold voltage of the cell transistor 101 and leads to junction leakage in a source/drain of the cell transistor 101, such that the prior art has a limitation in suppressing the off-leakage.
In accordance with another prior art to alleviate the above concerns, as illustrated in FIG. 2B, the device supplies the negative voltage, for example, negative word line voltage VBBW, lower than the ground voltage VSS, to the word lines WLs in a precharge operation mode, instead of supplying the back bias voltage VBB to the substrate.
However, when the word lines WL are supplied with negative voltage, a potential difference between the data storage unit 102 and the word lines WLs (or gates) is increased, which may lead to a gate induced drain leakage (GIDL). Since the GIDL becomes a major factor of the off-leakage as integration is increased, a semiconductor memory device staying in off state without the GIDL is in demand.